TPU SoC Integration Architect

The opportunity at Google Inc. centers on shaping the future of AI/ML hardware acceleration via TPU technology.

You will drive multi-chiplet SoC integration, architect RTL, and coordinate with Verification and Emulation teams to ensure robust silicon delivery for Google’s TPU family. As an ASIC SoC Integration Engineer, you’ll own RTL up to the package level, collaborate on interposer packaging, and plan multi-die DFT connectivity, while guiding cross-functional teams toward project milestones