Google is seeking a Hardware Engineer in Sunnyvale to lead TPU interconnect and packaging efforts, defining architectural strategy for 2.5D/3D interposers, embedded bridges, and CPO modules as part of next-generation TPU systems.
You will collaborate across silicon photonics, substrates, and system integration, drive full-lifecycle qualification, and partner with OSATs to deliver high-bandwidth, energy-efficient interconnects for AI/ML workloads.
#J-18808-LjbffrTPU Interconnect & Packaging Engineer (2.5D/3D) in sunnyvale at Unknown Company
This position is listed as full time and onsite.