Google in Sunnyvale, CA is seeking a mid-level RTL design engineer to shape the TPU microarchitecture and contribute to AI/ML hardware acceleration. You will design high-performance, power-efficient SystemVerilog RTL for complex digital designs and work to optimize for speed, power, and area.
You will collaborate with Verification and Physical Design teams to meet strict timing, area, power, and manufacturability requirements, while supporting post-silicon validation and cross-functional
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