Socket.dev is seeking an experienced hardware architect to lead the physical design of high-performance ASICs in Sunnyvale. You will guide from RTL to GDSII, coordinating with RTL, DFT, and packaging teams to ensure timing, power, and area targets are met in complex projects.
The role emphasizes technical leadership across subchip and top-level scopes, with influence on schedules, risk mitigation, and cross-functional collaboration with external vendors.
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