Synopsys, Inc. is seeking an experienced ASIC physical design engineer in Sunnyvale, CA.
You will drive timing closure, signoff readiness, and PPA optimization for advanced-node customer designs across block, subsystem, and chip levels. You will develop methodologies and automation using TCL, Python, or Pandas, perform static timing analysis with PrimeTime and ICC2, and collaborate with cross-functional teams to deliver silicon on time.
#J-18808-LjbffrStaff Physical Design Engineer: AI-Driven Timing & Automation in sunnyvale at Unknown Company
This position is listed as full time and onsite.