Google is shaping the future of AI/ML hardware acceleration through the design of its TPUs, the custom accelerators powering AI workloads in data centers. You will contribute to RTL IP development for chip-to-chip interconnects, participate in architecture decisions, and drive verification and integration within AI-driven systems.
As part of the inter-chip interconnect team, you will shape ASIC/SoC hardware for AI and networking accelerators that underpin Google's products, collaborating across
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