Google is seeking a seasoned Static Timing Engineer to join the chip implementation team in Sunnyvale, CA. You will contribute to constraint development, validation, and timing closure for large, high-performance compute ASICs.
You will develop static timing methodologies, margins, automation scripts, and write documentation, collaborating with architecture, logic design, and DFT teams to meet sign-off requirements. US: $ - $ (USD) + 15% bonus target + equity + benefits.
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