Synopsys, Inc. seeks an experienced ASIC physical design engineer to drive timing closure for advanced-node designs and lead signoff readiness across block, subsystem, and full-chip implementations.
You will build repeatable design flows using TCL, Python, and Perl, and work with PrimeTime, ICC2, Fusion Compiler, and Cadence tools, collaborating with CAD, verification, and frontend teams to ship silicon on schedule.
#J-18808-LjbffrSenior Staff Physical Design Engineer: AI-Driven Signoff in sunnyvale at Unknown Company
This position is listed as full time and onsite.