Senior SoC Physical Design Engineer - RTL-to-GDSII

Value Innovation Labs is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for low-power SoCs on advanced nodes. You will drive the full physical design flow from synthesis to GDSII, including floorplanning, placement, CTS, routing and timing closure.

You will handle SDC constraints and UPF promotion, develop automation flows with Tcl, Python and Shell, and mentor junior engineers while collaborating on design closure and signoff across the SoC hierarchy.