Hewlett Packard Enterprise Development LP in California is seeking a Senior Signal Integrity Engineer to join our onsite team. The role centers on COM/channel margin analysis, ASIC PAM4 SerDes modeling, and correlating simulations with measurements across packages, boards and connectors.
You will design PCB timing rules, tune SerDes channels up to 200G, perform DVT measurements, and collaborate with vendors to improve model accuracy. Advanced PAM4 experience and CAD tools are required.
#J-18808-LjbffrSenior Signal Integrity Engineer - PAM4 SerDes 200G in sunnyvale at Unknown Company
This position is listed as full time and onsite.