Senior RTL Subsystem Architect – SoC Design

Synopsys, Inc. is seeking an experienced RTL design leader to drive complex ASIC digital subsystems from concept to silicon. You will define architecture, translate requirements into clear specifications, and deliver high-quality RTL that is robust and scalable.

You will work across design, verification, DFT and implementation, with experience in UCIe, Ethernet, UALink, and AMBA. Mentoring junior engineers and leading design reviews are also key responsibilities.