Senior Power Integrity Engineer, Platforms InfrastructureDriving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. This is a specialized role which requires physical interaction with hardware equipment in a simulated data center environment, utilizing Google labs, power, and safety equipment. Regular development and processing of engineering hardware must be performed on site.Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience. 4 years of experience working in a system-level power delivery network design, analysis, and validation technical environment.
Experience with PCB, package and silicon technologies, and their impact on power delivery solutions.Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field. 1 year of experience in technical leadership.
Experience in die-to-PCB hardware validation and correlation, with the ability to script and automate lab measurements and EDA simulation workflows.
Experience in board, substrate package, and on-chip power integrity/conversion design for FPGAs, ASICs, or high performance processors.
Experience with industry-standard tools including Ansys (HFSS, Q3D, SIwave), Cadence (PowerSI/DC, Allegro, APD), CST, Keysight ADS, and Synopsys Hspice.
Experience in system-level PDN modeling, switching regulators, and data center motherboard power design, advanced voltage regulators, and next-gen components.As a Power Integrity Engineer within Platforms Infrastructure Engineering, you will play a pivotal role in developing one of the world's fastest-growing computing infrastructures. Working with a collaborative and high impact team, you will design, analyze, validate, and deliver robust and innovative power delivery network solutions at the chip, package, board, rack, and pod levels. Your work will directly shape our next generation AI hardware for AL/ML, server, networking, and storage applications.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $ - $ (USD) + 15% bonus target + equity + benefitsResponsibilities:Design system-level power delivery network solutions across silicon, substrate packaging, and printed circuit boards (PCBs).Partner with cross-functional teams to balance performance, cost, reliability, and availability trade-offs.Perform power integrity design validation, correlation studies, and root-cause analyses.Lead the triage and resolution of power integrity issues.Drive technology explorations into advanced power regulation and distribution, pioneering innovations across PCBs, chip packaging, and silicon.Engage with power module suppliers and industry partners to drive the development and evaluation of emerging power delivery technologies.Collaborate with EDA vendors to enhance simulation capabilities and methodologies.