We are looking for a Senior Physical Design Engineer with strong experience in RTL-to-GDSII implementation for low-power SoCs on advanced nodes.
- Drive physical design flow from synthesis to GDSII
- Floorplanning, placement, CTS, routing, and timing closure
- Handle SDC constraints and UPF promotion/pushdown
- Develop automation flows using Tcl, Python, and Shell
- Collaborate on design closure and signoff
- Mentor junior team members
- Contribute to flow and methodology improvements
- SoC hierarchy and integration
- Signoff flows and constraint management
Education:
B.Tech/M.Tech in ECE, EE, VLSI or related field
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