Senior Physical Design Engineer – High-Performance ASICs

Tachyum is seeking a Physical Design Engineer in Sunnyvale, CA to drive PD for ultra‑high performance chips. You will collaborate with RTL teams, perform floor‑planning, routing, and timing closure, and contribute to clock and power integrity strategies.

The role requires strong Verilog know‑how, ASIC flow experience, and a track record mentoring engineers. Expect a dynamic, cutting-edge environment with competitive compensation and equity.