Senior FPGA Engineer: RTL, Verification & Debug Lead

Celestica Inc. in Richardson, TX is seeking a Senior Staff FPGA Engineer to drive RTL design, verification, and back‑end flow for advanced hardware platform solutions.

You will collaborate with platform architects, board designers, and software teams to ensure robust delivery and timely debugging on real hardware. Required: 12+ years in FPGA design; strong Verilog/SystemVerilog; experience with Xilinx/Intel FPGAs, PCIe, DDR, LVDS; familiarity with UVM and ModelSim/Vivado/Quartus; excellent