Senior Design Verification Architect for SoC/IP

A semiconductor startup in Sunnyvale, CA is seeking a Principal Design Verification Engineer to own the verification strategy and execution for complex IPs or full-chip SoC. This role includes leading a team, establishing plans, and driving collaboration across various engineering teams. The ideal candidate will have 12–15 years of experience in ASIC/SoC design verification, a relevant degree, and expertise in SystemVerilog and UVM methodology. The position offers a compensation range of $250,000–$280,000, along with health coverage and equity options.
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