Senior ASIC Verification Lead (Hybrid)

Hewlett Packard Enterprise in Sunnyvale, CA is seeking a Principal ASIC Verification Engineer to join our networking silicon team. This hybrid role requires in-office presence two days per week.

You will own block- level verification, develop UVM environments, run constrained random testing, and collaborate with cross-functional teams to ensure high-quality ASIC/SoC deliverables. The role demands 15+ years in ASIC/SoC verification, SystemVerilog/UVM expertise, and proficiency with Cadence