Senior ASIC Timing & Sign-Off Engineer

Google is seeking a Static Timing Engineer for its chip implementation team in Sunnyvale. You will contribute to the physical implementation of ASICs, developing timing constraints, automation scripts, and performing timing closure for high-performance compute ASICs.

You will collaborate with architecture, logic design, and DFT teams, and evaluate vendors/tools to improve STA methodologies. Competitive compensation includes equity and benefits. Individual pay reflects skills and experience.