Senior ASIC Timing & Sign-off Engineer

Google is seeking a Static Timing Engineer to join the chip implementation team in Sunnyvale, CA. You will drive full-chip timing sign-off for high-performance ASICs, develop constraints, and automate STA flows using Tcl/Python/Bash, collaborating with architecture, logic design, and DFT teams to ensure robust timing and performance.

The role emphasizes building scalable timing methodologies, reviewing vendor/tool choices, and delivering reliable timing closures for industry-leading hardware