Cerebras Systems is seeking a Senior Front-End Design Engineer to lead RTL design for the Wafer Scale Engine. You will work with design verification, physical design, software and system teams to deliver high-performance, power-efficient chip implementations from concept to production.
The role requires a Master’s degree in CS/EE and 8+ years of experience in RTL designs, with strong experience in front-end chip integration, networking, and collaboration with external vendors.
#J-18808-LjbffrSenior ASIC RTL Design Engineer - Hybrid/Remote in sunnyvale at Unknown Company
This position is listed as full time and onsite.