Google is seeking an ASIC Design Engineer to shape AI/ML hardware acceleration by developing power-efficient TPU architectures and associated power models. You will verify complex digital designs and contribute to power optimization strategies within TPU projects and data-center accelerators.
The role involves collaborating with cross-functional teams to drive power efficiency from design through verification, impacting Google's cutting-edge AI hardware used globally.
#J-18808-LjbffrSenior ASIC Power Architect for ML Accelerators in sunnyvale at Unknown Company
This position is listed as full time and onsite.