Senior ASIC PD Engineer for TPU AI Hardware

Google LLC in Sunnyvale, CA, USA seeks a Share Senior ASIC Physical Design Engineer to drive the PD of TPU blocks from RTL to GDSII. You will collaborate with RTL, DFT, floorplanning, and full-chip signoff teams to optimize power, performance, and area while evaluating new micro-architectures and practical logic solutions.

The role requires working closely with external partners on PD closure and understanding STA, timing corners, derates, and PnR flows using Synopsys/Cadence tools.