Senior ASIC DFT Engineer for High-Performance SoCs

Meta is seeking an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team. You will architect testability solutions for large-scale ASICs and drive DFT strategies from RTL to silicon bring-up.

Responsibilities include achieving high fault coverage across multiple fault models, supporting silicon bring-up and manufacturing test, and collaborating with design, physical implementation, and validation teams to deliver testable silicon at scale.