Hewlett Packard Enterprise in Sunnyvale, CA, onsite role focused on designing high-speed ASICs. You will develop micro-architecture from specs, implement RTL in Verilog/SystemVerilog, and drive verification with coverage and assertions.
You will work with Physical Design and Verification teams to meet timing and validation goals while mentoring new engineers. Join a fast-paced silicon group that builds leading networking chips, with opportunities to grow leadership skills and contribute to
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