Google Sunnyvale, CA, is seeking an experienced RTL design engineer to shape the future of AI/ML hardware acceleration. You will drive TPU architecture, design RTL IP for ASIC products, and collaborate with software and system hardware teams to bring complex digital designs from concept to production.
The role focuses on SoC RTL design for data center accelerators, clocking and reset management, integration with software, and collaboration across multiple teams to deliver scalable AI solutions.
#J-18808-LjbffrRTL Design Engineer for TPU ASIC – AI Hardware in sunnyvale at Unknown Company
This position is listed as full time and onsite.