Micron Technology, Inc. is seeking a hands‑on SoC Physical Design Engineer within the Heterogeneous Integration Group to drive implementation from netlist to GDSII. You will collaborate across RTL, DFT, IP, packaging and manufacturing to ensure best-in-class PPA and robust signoff for tape-out.
The role emphasizes floor-planning, placement, CTS, routing, timing/power integrity, and post‑silicon debug. A strong background in advanced-node PD and DFT coordination is required.
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This position is listed as full time and onsite.