Meta is hiring a Design Verification lead to own verification for complex computer vision and imaging accelerator IP and subsystems. You will define the verification strategy across multiple IPs and build scalable DV infrastructure spanning chips and programs.
The role requires 8+ years in SystemVerilog/UVM/C++, leadership experience, and deep verification expertise across SoC tape-out, formal methods, emulation, or low-power verification.
#J-18808-LjbffrLead Design Verification Engineer for AR Vision & Imaging in sunnyvale at Unknown Company
This position is listed as full time and onsite.