Lead ASIC Digital Design Engineer for LPDDR PHY

Synopsys Inc. is seeking an experienced ASIC digital design engineer to own RTL for LPDDR PHY IP. You will design RTL modules from microarchitecture through synthesis-ready implementation and optimize for timing, power, and area across multiple nodes.

You will develop Perl automation for design generation, collaborate with cross-functional teams, and contribute to design reviews. A strong background in Verilog, synthesis, and timing analysis is required, with 8+ years in production silicon.