Hybrid Senior ASIC Verification Engineer – Networking

Hewlett Packard Enterprise in Sunnyvale, CA is seeking a Senior ASIC Verification Engineer for a hybrid role requiring 2 days per week in the office. You will own block- or subsystem-verification efforts, build and maintain UVM environments, and drive coverage closure for complex SoCs.

Ideal candidates bring strong SystemVerilog/UVM skills, extensive ASIC/SoC verification experience, and proficiency with Cadence Xcelium, Synopsys VCS, and Mentor Questa.