Hybrid Senior ASIC Verification Architect

Hewlett Packard Enterprise in Sunnyvale, CA, is seeking a Senior ASIC Verification Engineer to lead block- and subsystem-verification efforts within a fast-paced silicon group. You will craft test plans, build and maintain UVM environments, and drive coverage to closure in a collaborative setting.

Responsibilities include constraint-driven random testing, debugging complex SoCs, and using Cadence Xcelium, Synopsys VCS, and Mentor Questa to validate designs.