Google is seeking an ASIC Design Verification Technical Lead in Sunnyvale to shape the verification strategy for high-speed TPU technology powering AI workloads. You will design constrained-random verification environments and drive emulation and post-silicon correlation, ensuring RTL matches architectural specs in large-scale data centers.
You will lead cross-functional teams of DSP engineers and algorithm developers, define verification architectures, and push advanced methodologies from pre-
#J-18808-Ljbffr