Wireless PHY Verification Engineer – RTL/UVM Specialist

Apple seeks a PHY Design Verification Engineer in the San Francisco Bay Area to contribute to wireless silicon development and DV methodology. You will build and run constrained-random tests, develop test benches, and verify pre-silicon RTL for wireless PHY interfaces, collaborating with RF/Analog, Systems, and FW teams.

Preferred skills include Verilog/SystemVerilog/UVM, Matlab, and FPGA validation, with a background in ASIC verification flows and test coverage.