Wireless ASIC Verification Engineer (UVM, Verilog)

A leading technology firm in Austin, Texas, is seeking a skilled engineer to join Project Kuiper. In this role, you will implement a verification environment and participate in validation processes and system-level verification using UVM. The ideal candidate possesses a Bachelor's degree in Electrical / Communications Engineering or Computer Science, along with a minimum of 2 years of experience in verification and UVM. This position offers a unique opportunity to contribute to groundbreaking satellite communication technology.
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