VLSI Design Engineer – Timing & P&R Expert

TSMC Technology, Inc. in San Jose, California is seeking a Design Engineer to address DRC/LVS/EMIR issues, optimize floorplans and timing ECOs for high-performance blocks.

The role involves clock tree customization, floorplan, place and route, and signoff responsibilities. The candidate should hold a Master’s degree in Electrical or Computer Engineering, with strong experience in RTL coding, digital design, and state‑of‑the‑art EDA flows such as Cadence Innovus and Virtuoso.