VLSI Design Engineer: DRC/LVS, Timing & ECOs

TSMC Technology, Inc. in San Jose, CA seeks a Design Engineer to perform DRC/LVS/ANTENNA analysis, fix violations, and support timing closure for high-performance blocks. The role involves clock tree customization, ECOs, floorplanning, and thorough documentation of methodologies.

You will work on power/EM analysis, signal integrity checks, and signoff tasks while sharing best practices with the team to improve overall efficiency and collaboration.