ByteDance is seeking an ASIC Design Engineer for the Video Silicon IP team to design high-performance video codec hardware (FPGA/ASIC). You will work with architecture, algorithm, software and verification peers to deliver scalable video processing IPs and meet strict PPA targets across multi-standard codecs.
The role requires SystemVerilog/Verilog RTL design, RTL ownership, and collaboration to translate codec specs into efficient hardware architectures; familiarity with UVM/DPI/C++ is a plus.
#J-18808-LjbffrVideo Silicon IP ASIC Design Engineer in san jose at Unknown Company
This position is listed as full time and onsite.