ByteDance’s team in California is seeking a design verification engineer to help deliver a Video Codec IP for FPGA/ASIC platforms. You will generate test benches, run simulations, and debug TB/Design issues with a collaborative team of architects, FPGA/ASIC designers, and verification experts.
The role emphasizes hands-on regression testing, test plan creation, bug tracking leadership, and waveform analysis using VCS and Verdi to ensure high quality, scalable video processing engines within a
#J-18808-LjbffrVideo Codec ASIC Verification Engineer in san jose at Unknown Company
This position is listed as full time and onsite.