ByteDance is hiring ASIC design engineers to build high-performance video codec hardware IP (FPGA/ASIC) in the Video Silicon IP team in San Jose. You will work with architecture, algorithm, software, and hardware teams to meet tight PPA targets and deliver scalable video processing hardware.
The role emphasizes collaboration across RTL design, verification, synthesis, and physical design, as well as Python scripting for automation and exposure to modern video codecs.
#J-18808-Ljbffr