Verification Engineer, SoC/ASIC | UVM & SystemVerilog

Efficient Computer is hiring a Design Verification Engineer to own the functional verification of blocks and subsystems in our SoC. You will work with senior DV engineers, RTL designers, and architects to build testbenches, close coverage, and find bugs before silicon ships.

This role offers growth as we move from initial product development to market release and scaled volume production, with a strong emphasis on automation, coverage, and sign-off readiness.