IMC is seeking a Verification Engineer to join its R&D team in Chicago. You will verify complex hardware designs using UVM, collaborate with RTL and SW teams, and automate verification flows for rapid development.
The role requires experience with SystemVerilog/Verilog, C++, scripting, and Linux, plus familiarity with 3rd party EDA tools. The position offers a competitive base salary, discretionary bonus eligibility, and benefits including paid leave and insurance.
#J-18808-LjbffrVerification Engineer: Automated HDL Validation in chicago at Unknown Company
This position is listed as full time and onsite.