Mixed-Signal Design Verification EngineerLocation: San Jose, CA 100% OnsiteQualifications:Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc.Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog-A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters, CDR.,)Familiarity with behavioral Verilog code for an analog circuitAbility to write thorough test benches for digital and AMS simulatorsDeep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gatingFamiliarity with timing closure and static timing analysis toolsExperience with scan chain vector generation and verificationResponsibilities:Extract modeling specifications from designersDevelopment of Analog/Mixed-Signal model in System-VerilogDevelopment of UVM Testbench and developing test casesRun simulation and fix the behavioral model working with Circuit designer.Develop timing model for the circuit working with layout engineer.This role will provide the ability to directly influence design related changes as required to meet functional specificationsDetermine whether anomalous symptoms are caused by errors in the specifications, models, testbench, or designSupport integration of composite models into larger composite models maintained by other groupsPreferred Skills:UVM/System Verilog (Priority: 1)Python (Priority: 2)Synopsys/Cadence EDA Verifications Tools (Priority: 1)AMS Verification (Priority: 1)