Post Silicon Validation EngineerLocation: San Jose, CA, Hybrid option allowedQualifications:BSEE, MSEE (or higher) preferred, in Electrical Engineering.Strong background in SOC/VLSI/Mixed Signal IC bring-up, production and characterization test, and product engineering.Strong fundamentals in IC design, Design for Test, and manufacturing concepts.Low level C, C++, RISV-V assembler, micro coding, Python, and familiarity with either Verilog, VHDL and SystemRDLAbility to debug hardware using lab equipmentKnowledge of test cell integration and production test program releaseProven understanding of the latest DFT and test solutions.Ability to thrive in a multifaceted environmentHigh level of motivation and energyHands on experience with one or more of the following:RISC-VNetwork On Chip IPsMemory Controller IPs (DDR5)Low power testingPCIe and CXL (testing)UCIeFamiliarity with FPGAsUse of Logic Analyzer, scope and in general HW/FW integration and debuggingRoles/Responsibilities:Working with custom network processors, transceivers, mixed signal ICs, multi-die modules, bare die, and stacked die.Drive the post-silicon validation cycle to meet Product Quality and Time to Market Metrics.In a multi-function team, you will define and develop test plans for optimized test.Design and Develop testability requirements in close partnership with IP and design teams and influence implementation of test features.Craft test hardware, bring up test, and release test programs to production.Develop test requirements for ground-breaking IP, to minimize test overhead both in design and for production.Develop custom test solutions spanning high power, large dies, and packages to cost-sensitive products.Expertise with Advantest 93K to drive to lower test costs via optimized test implementation.Work closely with OSATs to set up test infrastructure as well as deploy test programs for production.C/C++ (Priority: 2) Python (Priority: 2) Verilog/VHDL (Priority: 1) Silicon Validation tools (Priority: 1)