DFT EngineerPossible 3 Month CTH | No Fees | Do Not Re-Post | Confidential Submit candidates under their legal name and use only Capgemini templateRole: DFT EngineerWork Location: Santa Clara, CARate: $85.00/hrQualification/Experience/Skills Required:Ability to define and describe (write specification for) system architecture, external interfaces, register definitions and operations, major partitionsAbility to write clear, concise documents and diagrams (timing, state machines, register maps, memory organization, synchronization sequences, etc.) to describe functional and operational (parametric) aspects of a complex SoCDomain knowledge of various software applications and their underlying hardware requirements (e.g., networking, AI, Machine Learning, storage devices, IoT)Experience in Digital module design and micro-architectureExperienced at modeling complex state machines, data-paths and bus protocols/high speed (bandwidth) interfaces such as PCIe3+ years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SoCsStrong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBISTExperience with Synopsys DFT Complier, Tetramax and VCS is requiredExperience with TestKompress, Tessent and Modus/Encounter tool suite is a plusExperience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metricsHands-on expertise in writing System Verilog and VHDLHands-on in Perl/Tcl/Unix scriptingExcellent analytical, and problem-solving skills8+ years' industry experience, Master's degree or equivalent in EE or Computer Engineering (CE)Roles & Responsibilities:Write clear, concise specification for an SoC including functional and timing descriptions for top level pins/ports/interfaces, registers and memories, state machines, datapaths, operating modes, exception/error handling, clocking, reset, power domains, etc.Describe parametric/operating environment requirements including performance, power, area (PPA) targets, temperature and process ranges, IO pads, parametric tests, etc.Interact with other system architects to define the application environment for the SoC being designed (firmware and OS requirements, external storage devices, sensor/analog components, etc.)Provide SoC (top) level constraints and partitions for RTL/Logic designers, floorplan & PD engineers, DFT requirementsPerform top/block-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulationVerify DFT circuitry and interface with other blocks, debug timing simulation issuesClosely work with physical design team to generate and validate timing constraintsBe able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learningBe able to work independently and own the complete task from DFT specification to final pattern delivery for sub-system and/or SOCWorking closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals, functional and diagnostics test coverageTechnical interaction with engineering teamEducation: BSEE, in Electrical/Computer OR MSEE, in (Electrical/Computer)