Annapurna Labs (U.S.) Inc. seeks an ASIC Design Engineer to drive high-performance, power-efficient RTL designs for AWS inference servers.
You will create SystemVerilog RTL, analyze architectures, and collaborate with cross-functional teams to ensure design quality and timely delivery. The role requires a strong ASIC design background, proficiency in SystemVerilog, and excellent analytical and problem-solving skills.
#J-18808-LjbffrTrailblazing ASIC Design Engineer II in cupertino at Unknown Company
This position is listed as full time and onsite.