TPU RTL Design Engineer for AI Accelerators

Google in Sunnyvale seeks an RTL Design Engineer to shape the TPU microarchitecture and deliver high-quality SystemVerilog RTL for AI/ML accelerators. You will drive design decisions that balance performance, power, and area while collaborating with Verification and Physical Design to meet timing and manufacturability requirements.

You’ll own critical design deliverables, partner with DV and PD teams across the TPU ecosystem, and contribute to post-silicon validation and integration.