Top-Level SoC Physical Design Engineer — Drive Tapeout

Apple Inc. in Beaverton, Oregon seeks an experienced chip design professional to drive full-flow ASIC/SoC implementation from netlist to tapeout. You will partner with FE and physical design teams to set goals, guidelines, and milestones for place and route, timing, and IP integration.

Responsibilities include floorplanning, power distribution, global timing, and multi‑domain convergence for large designs (>20M gates) at >1GHz, using sub‑45nm tech. BS plus 10+ years required.