ACL Digital is seeking a Senior Principal Physical Design Engineer to take ownership of the top-level floorplan and global power networks for its next-generation architecture.
The ideal candidate will have proven expertise in full-chip integration, mastery of Cadence Innovus and Synopsys Fusion Compiler, and the ability to manage timing budgets and EM/IR sign-off workflows. Exceptional collaboration skills are essential to work closely with both internal and external teams.
#J-18808-LjbffrTop-Level PD Architect: Chip Floorplan & Power in san jose at Unknown Company
This position is listed as full time and onsite.