Apple in Sacramento, CA is seeking a Timing Design Engineer on a part-time basis. The role focuses on block-level static timing analysis, clock networks, and timing closure for high-performance SOCs. Strong Verilog and STA experience are required.
You will collaborate with RTL/PD teams, generate ECOs, and help refine CAD methodologies while benefiting from comprehensive health, retirement, and stock options. Apple emphasizes growth support and educational reimbursements.
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