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Technical Staff Engineer - Analog Design (SRAM Design)

los gatos, ca • Posted 1 weeks ago
Onsite Full Time General

Technical Staff Engineer – Analog Design (SRAM Design)Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM).

We also license Flash-IP solutions that are incorporated in a broad range of products.Microchip Technology Inc. has a Technical Staff Engineer – Analog Design (SRAM Design) opening based in San Jose, California. The successful candidate will be responsible for the design of complex, multiport SRAM blocks with many programmable features and modes for use in advanced and low power FPGA devices.

In this role, you will be working within a team of other circuit design engineers and collaborating with architecture, ASIC, firmware, verification, and test teams to help deliver industry-leading FPGA products.Responsibilities:Define, estimate, develop, and optimize full custom high speed SRAM block for speed, low power, area, and feature setEstimate speed and power for various memory configurations and memory cell typesDefine internal memory array architecture for redundancy, ECC compliance, and optimal speed with lowest powerAnalyze projected SRAM yield per device versus redundancy requirementsRun experiments using memory compilers from EDA vendors for embedded memories to evaluate PPA trade-offs of device mixCreation and verification of circuit schematics and functional Verilog modelsSimulate and evaluate SRAM cell for cell stability, write and read margin, minimum cell operating and state retention supply level, and noise marginSimulate and analyze critical paths and all features and functionsOptimize memory array and non-array logic transistor sizes and Vt selection for lowest possible dynamic and standby powerDevelop and optimize sense amps for reliable operation, high speed, low power, and sufficient noise marginDesign testability circuitry and define SRAM test requirementsWrite technical specifications and participate in formal reviews of other block specificationsContribute to datasheet development through block characterizationEngage in design and verification of other circuit blocks outside of SRAMSupport verification and timing characterization teamsDrive and participate in silicon validation of SRAM blocks for functionality and performanceRequirements/Qualifications:Bachelor's degree in Computer Engineering, Electrical Engineering, or Computer Science12+ years of experience in custom SRAM design and/or memory circuit designHigh degree of SPICE simulation proficiencyAdept at leveraging full custom design EDA tool setDemonstrated competency in scripting, managing simulation queues, data capture and analysisProficient in simulating and analyzing yield impact, reliability, and powerAbility to support layout, verification, timing characterization, and software model developersAbility to develop and test Verilog simulation model and compare back to SPICE based modelExcellent analytical, communication (written and verbal), and documentation skillsSelf-motivated and proactive team playerAttention to detail and ability to drive tasks to completion independently in timely mannerPreferred Qualifications:Master's degree in Computer Engineering, Electrical Engineering, or Computer ScienceExperience in analog and full custom designExperience in FPGA or ASIC developmentExperience in functional verification and timing characterizationExperience in low power design including dual rail, array biasing, dynamic low power mode switching (sleep, power gating, column array muxing)Experience in OCV timing and yield variation analyses using Solido and Monte CarloTravel Time:0% - 25%Physical Attributes:Feeling, Hearing, Other, Seeing, Talking, Works Alone, Works Around OthersPhysical Requirements:10% sitting, 10% walking, 80% sitting, 100% in doors; Usual business hoursPay Range:The annual base salary range for this position, which could be performed in the US, is $91,000 - $232,000.**Range is dependent on numerous factors including job location, skills and experience.Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

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