Technical Project Lead - Research

ASML US brings together the most creative minds in science and technology to develop lithography machines that are key to producing faster, cheaper, more energy-efficient microchips. We design, develop, integrate, market and service these advanced machines, which enable our customers - the world’s leading chipmakers - to reduce the size and increase the functionality of their microchips, which in turn leads to smaller, more powerful consumer electronics. Our headquarters are in Veldhoven, the Netherlands, and we have 18 office locations around the United States including main offices in Wilton, CT, Chandler, AZ, San Jose, CA and San Diego, CA.

The Technical Project Lead, Main Deliverable Owner, is responsible for managing the critical path of key project deliverables, while balancing the triple constraints of schedule, resources and cost.

This includes but is not limited to creating and tracking schedules, performance targets, resources plans, and general planning activities for Source Research (SR) learning and testing deliverables. Throughout the process, the MDO is responsible for ensuring that the proper elements of the SR WOW are known and adhered to across the research team: assessing risk and mitigation strategies; highlighting issues and managing their solutions including through escalation process; and coordinating the various development activities to ensure intermediate cross-program communication. The MDO makes the connection between high-level plans and tactical, operational plans.

Duties and responsibilities

• Manage system hardware and software integration and completion of technical learning deliverables from SR Functions Own deliverables (qualified BoM/SW baseline; qualified build/setup & test sequence; qualified upgrade packages, integration sequence)
• Align on triple constraints, with the relevant stakeholders internally and across sectors - Safety, Facilities, Operations, Manufacturing, Engineering
• Report on deliverable status and quality, towards project lead, program and line management
• Own release strategy for baseline and upgrades with team and roll up to high-level plan with the Project Lead.
• Own the "bottom-up" plan
• Plan work over prototype EUV light sources (test rigs)
• Manage bottom-up differences between machine plans and integration plan
• Report on bottom-up differences between machine and integration plan
• Manage critical path of hardware and software integration
• Support and monitor test preparation and readiness, including documentation, materials tracking, tool availability, sequence generation, test plan reviews and resources
• Provides input towards the SR learning objectives and committed testing
• Manage issues for the agreed deliverables
• Roll-up towards Top-X lists & report
• Proto test rig level impact
• Define and own the issue handling WOW, maintain issue lists (or delegate), ensure root cause corrective actions are completed
• Critical stakeholder for equipment availability and utilization, maximizing learning potential through lessons learned and test operational reports
• Report on integration quality towards internal customers and make proposals for structural improvements
• Plan, coordinate and coach the assigned test engineering team in order to identify and separate integration related product risks compared to issues as a result of research efforts
• Performs other duties as assigned